1. Field of the Invention
The present invention relates to a multilayer chip capacitor, and more particularly, to a multilayer chip capacitor, which is suitable to be used as a decoupling capacitor of a power distribution network of a micro processor unit (MPU), can improve equivalent series resistance (ESR), and can maintain a constant impedance around a series resonance frequency (SRF).
2. Description of the Related Art
An operating frequency for a high-speed microprocessor unit (MPU) is steadily increasing, leading to an increase in current consumption, and an operating voltage for an MPU chip is decreasing. Thus, it becomes more difficult to suppress noise of a DC supply voltage, which occurs due to a sudden fluctuation of a load current of the MPU, below a certain level, generally, 5 ˜10%. A multilayer chip capacitor for decoupling is being widely used in a power distribution network (PDN) of the MPU in order to remove the voltage noise. The multilayer chip capacitor used as a decoupling capacitor suppresses voltage noise by supplying a current to a central processing unit (i.e., an MPU chip) at the time of the sudden fluctuation of the load current.
The load current fluctuates even more rapidly with a further increase in operating frequency of the MPU. Therefore, a decoupling capacitor is required to have higher capacitance, higher equivalent series resistance (ESR) and lower equivalent series inductance (ESL), so that a low and constant impedance of the power distribution network can be maintained in a wide frequency range. This can ultimately contribute to suppressing the voltage noise caused by the sudden fluctuation of the load current.
To satisfy the low ESL characteristic required in a decoupling capacitor used for the PDN of the MPU, modifications in locations or shapes of external electrodes or shapes of internal electrodes have been proposed. For example, U.S. Pat. Nos. 5,880,925 and 6,407,904 disclose a method for reducing the ESL and changing a current path within a capacitor by disposing leads of first and second internal electrodes of opposite polarity adjacent to each other in an interdigitated arrangement.
Such relate dart techniques may contribute to reduction of the ESL, but undesirably cause the ESR to decrease. The capacitor having the aforementioned structure may be helpful in lowering the high-frequency impedance. However, because of the insufficient ESR, the capacitor fails to maintain the low and constant impedance in the PDN.
To overcome the insufficient ESR, a method for implementing high ESR by using a high-resistance electrical material for an external electrode or an internal electrode has been proposed. However, if a high-resistance external electrode is used, a localized heat spot resulting from current concentration caused by a pinhole within the external electrode must be prevented, and it becomes difficult to precisely adjust the ESR. Also, if an internal electrode of a high-resistance material that must match with a ceramic material is used, the high-resistance material of the internal electrode must be changed continuously according to improvements or modifications in the ceramic material for a higher capacitance of a capacitor. This may cause the unit cost of a product to increase.
U.S. Pat. No. 7,251,115 discloses a capacitor that can achieve the low impedance over a wide frequency range by disposing two capacitors having different capacities within one capacitor body. However, as disclosed in this application, the constant impedance cannot be maintained around each series resonance frequency (SRF), and thus the stability of a power circuit degrades.